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A good question
is a place to start.

One RTL block.

A focused evaluation for an owned, synthesizable block with a stable interface and a defined ASIC or FPGA flow.

For research or work outside RTL, describe the current baseline, the constraints that must hold, and the measure you would like to improve.

A short, non-confidential description is enough for the first conversation. Please do not attach confidential RTL, credentials or production data.